It is often desirable to improve the efficiency and comprehensiveness of manufacturing testing of computer components. To ensure fast and reliable operation of a computer, manufacturing testing of each part must include some form of speed testing to show that the component is operating within the specified timing parameters.
One type of testing performed during semiconductor fabrication is a wafer test. Wafer tests are conducted on a wafer of a semiconductor chip prior to the wafer being sent to die preparation. The wafer includes all of the individual integrated circuits of the chip design such that functional defects of the chip may be detected through the wafer test. If a defect of the die is determined through the wafer test, the die may not be mounted on a package, thus saving the costs associated with packaging.
To perform the wafer test, the integrated circuit may be connected to a wafer prober. In general, the wafer prober provides the power to run the test and utilizes several probes to obtain the results of the test. However, in many instances, the wafer prober cannot provide the chip design of the wafer with enough current to conduct at-speed testing of the chip. In other words, the chip design may require a certain amount of current to perform at the designed operating speed of the chip. This current level is often not available during the wafer test as the wafer prober (or other wafer testing devices) is not capable of providing the necessary current. As such, many wafer tests are conducted at clock speed that is far less than the normal operating speed of the chip. Other methods for improving the at-speed testing of the wafer include only testing one or more portions of the chip separately in an attempt to improve the clock speed used during the test. However, such solutions are not capable to providing accurate test results at the normal operating speed of the chip design.
It is with these and other issues in mind that various aspects of the present disclosure were developed.